In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, and etching. Such techniques are described in S. M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
The dimensions of the features and spaces depend on the resolution capability of the lithographic systems. The minimum feature size (F) achieved by a given generation of lithographic systems is referred to as the lithographic groundrule. As device manufacturers are continually pressured to increase the density of devices per chip while decreasing chip size, the placement or layout of devices becomes more important. An effective technique of decreasing chip size without changing the design rule is to fabricate devices in a three-dimensional design layout instead of the conventional two-dimensional format. In the three-dimensional layout, devices are fabricated over other devices. As a result, vertical and horizontal integration of devices is achieved, thus utilizing chip area more efficiently than the two-dimensional layout which only integrates the devices horizontally.
Certain factors are taken into consideration in order to determine the layout of the devices. These factors include the type and quality of material on which the devices are fabricated. As an illustration, certain devices, such as an access transistor in a dynamic random access memory (DRAM) cell, are fabricated on single crystalline material with low defect density due to their performance needs. The high carrier mobility and low leakage currents associated with the single crystalline material having low defect density satisfies the performance requirements of such devices.
However, the need to fabricate certain devices on high quality single crystalline material limits the effectiveness of three-dimensional design layouts. Some devices, such as trench capacitors, are formed with polycrystalline (poly) material. Unfortunately, the poly does not provide an adequate base for devices with high operating performance requirements. Such devices, in conventional design layouts, are located in areas next to the trench capacitors where single crystalline material exists, thus limiting the size-reducing effect of three-dimensional design layouts.
From the above discussion, it is apparent that there is a need to increase the available area of high quality silicon for improved three-dimensional integration of devices.